1. Field of the Invention
The present invention relates to a dot matrix type liquid crystal display, and in particular, an active matrix type liquid crystal display where the polarity of the write voltage which is applied to the liquid crystal cell is inverted after every plurality of scan lines.
2. Description of the Related Art
Of the liquid crystal displays commonly used, types such as STN (Super Twisted Nematic) and TFT (Thin Film Transistor) are representative. Of these types, an STN type liquid crystal display uses a passive matrix drive. In other words, with a passive matrix drive, the liquid crystal panel is constructed of electrodes and liquid crystal without the provision of switching elements, and the liquid crystal of each pixel positioned in the matrix is driven with time-division in synchronization with a scan signal.
In contrast, TFT type liquid crystal displays are active matrix driven. In other words, with an active matrix drive, by positioning switching elements comprising active elements such as TFTs at each pixel, it becomes possible to isolate the ON pixels and the OFF pixels and hold the voltage applied to the ON pixels, and drive with time division and synchronize the liquid crystal of each pixel positioned in the matrix with a scan signal. Because this method offers good contrast and response, and high image quality and large displays can be easily realized, recently active matrix type liquid crystal displays have become predominant.
From this point, discussion will center on active matrix type liquid crystal displays. Firstly, liquid crystal displays use a line-sequential driving method, where a single screen image is displayed by driving the scan lines in sequence from the uppermost scan line toward the lowest scan line. Moreover, this one screen is generally called a frame (or a field). Furthermore, in a liquid crystal display, when the liquid crystal cells are driven, in order to prevent the liquid crystal material from deteriorating, the polarity of the write voltage applied to the liquid crystal cells is inverted after a predetermined amount of time elapses, resulting in driving by an alternating current.
Here, the timing of the inversion of the polarity of the write voltage can be performed on either a frame by frame basis, a scan line by scan line basis, or a pixel (dot) by pixel basis, and these are known as frame inversion drive, line inversion drive and dot inversion drive respectively. Of these methods, the most fundamental driving method is frame inversion drive, where the polarity of the write voltage to be applied to each pixel is changed for every frame. In other words, if a specific pixel in a certain frame is driven with a positive polarity, then after the driving of the whole frame has been performed, if the same pixel is to be driven again, it will be driven with a negative polarity.
In contrast, line inversion drive and dot inversion drive are methods where the polarity can be inverted even within one frame. Of these, with line inversion drive (more accurately, one line inversion drive), if a certain scan line is driven with positive polarity, then the next scan line directly below this scan line is driven with negative polarity, and the following scan line is again driven with positive polarity. Dot inversion drive is a method where the polarity is inverted for every pixel on each scan line, and with two adjacent liquid crystal cells as a unit, the polarity of the write voltage is changed alternately.
However, when the polarity of the write voltage has been inverted, it is necessary for the drain line for supplying this write voltage to the liquid crystal cell to be charged from a negative polarity voltage to a positive polarity voltage, or alternatively, discharged from a positive polarity voltage to a negative polarity voltage. Consequently, with line inversion drive, the charging and discharging of the drain lines is performed frequently, and power consumption increases. Hence, if the polarity of the write voltage is inverted for each single scan line as described above, then the increase in power consumption will be quite marked.
If frame inversion drive is used, then power consumption can be reduced, but because in this case voltage of the same polarity is continually held in the liquid crystal cell for the period of one frame, a different problem occurs in that the display level of the pixel is disrupted by current leakage from the TFT. Because of this, recently as a compromise, “Multiple Line Inversion Drive” where the polarity of the write voltage is inverted after every plurality of lines is beginning to be used. However, in this type of multiple line inversion drive also, there are problems as described below.
Here, FIG. 9 shows the structure of essential sections of a liquid crystal display according to related art, and here only those matters pertaining to the problems of this related art will be described. Firstly, each pixel comprises a TFT 100 and a liquid crystal cell 101 as shown in the figure. Each pixel is placed at a point of intersection between a plurality of gate lines 102 which run in rows (the scanning direction) and a plurality of drain lines 103 which run in columns, and these pixels form a liquid crystal panel 104.
A gate driver 105, by sequentially supplying a drive voltage to the gate line 102, controls the conduction state of the TFTs 100 which are connected to each gate line. Furthermore, a source driver 106, by supplying a write voltage to the drain line 103, conducts writing to each of the liquid crystal cells 101 via the TFT 100 driven by the gate driver 105. Moreover, a timing controller 107 transmits a variety of control signals to the gate driver 105 and the source driver 106. Furthermore, a fixed voltage is applied to a common electrode 108, which is connected to one end of the liquid crystal cell 101.
Next, FIG. 10 shows a timing waveform of the liquid crystal display shown in FIG. 9 when a two line inversion drive is used. In the figure, a clock signal VCK is used by the gate driver 105 to sequentially activate the gate lines 102. Furthermore, a latch pulse signal STB is a timing signal for transmitting one scan line of image data taken into the source driver 106 to the drain line 103. Here, in the frame directly before the frame corresponding with the timing shown in FIG. 10, a write voltage of a negative polarity is assumed to have been applied to the nth and the nth+1 scan lines. Moreover, the nth scan line (gate line) will be referred to simply as the n line in the following description, and the other scan lines will be referred to in the same manner.
Firstly, when the clock signal VCK rises at time t100, the drive voltage shown as the “n line gate waveform” is applied to the n line, and the pixels connected to this gate line are selected. Next, when the latch pulse signal STB falls at time t101, the write voltage corresponding with the image data on the n line is applied to the drain line 103, and writing commences to the liquid crystal cell 101 which is connected to this n line.
However, this case describes the situation immediately following an inversion of the polarity of the write voltage, and in addition to the capacity of the liquid crystal cell 101 the capacity of the drain line 103 must also be charged (or in the case of the transition from write voltage of a positive polarity to write voltage of a negative polarity, must be discharged). Consequently, the voltage of the drain line 103 gradually rises from a write voltage of a negative polarity to a write voltage of a positive polarity, until a time t102 when the rise of the voltage finally stops.
Subsequently, when a time t103 is reached following the elapsing of a time T, which corresponds to one horizontal period on the screen, from the time t100, the drive voltage is no longer applied to the n line, and instead the drive voltage represented by the “n+1 line gate waveform” is applied to the n+1 line. Next, when the latch pulse signal STB falls at a time t104, then in the same manner as with the n line, the write voltage corresponding with the image data is supplied to the drain line 103.
In fact, at this point in time, the drain line 103 has already been charged to voltage of a positive polarity by the writing to the n line. Consequently, only the capacity of the liquid crystal cell 101 needs to be charged (or discharged) in the n+1 line, and the drain line waveform becomes a flat waveform which remains at approximately the same electrical potential. When the latch pulse signal STB falls at a time t105 which is reached following the elapsing of the time T from time t104, the voltage of the drain line 3 changes from a voltage of a positive polarity to a voltage of a negative polarity for writing to the n+2 line.
As described above, because extra time is taken in the n line to charge the capacity of the drain line 103, waveform dullness occurs in the rising portion of the drain line waveform (time t101–t102). In contrast, because there is no need to charge the capacity of the drain line 103 in the n+1 line, waveform dullness such as that observed in the case of the n line does not occur (time t104-).
Regardless of these differences, in liquid crystal displays according to related art, each of the gate lines is driven in the same manner, and the write period for each scan line is always fixed as the time T. Therefore, for example, the write states of the liquid crystal cells 101 of the n line and the n+1 line differ. In other words, the holding voltage of the liquid crystal cell connected to the n+1 line reaches the voltage corresponding with the image data output by the source driver 106 because the write period is sufficient. In contrast, the holding voltage of the liquid crystal cell connected to the n line does not reach the voltage corresponding with the image data because a sufficiently substantial write period cannot be secured due to the effects of waveform dullness.
Here, because if the holding voltage of the liquid crystal is lower the brightness of the pixels is that much lower, the brightness of the n line will be lower than the brightness of the n+1 line. Because this phenomenon also occurs in the other scan lines, the brightness of the pixels can differ for each scan line, and on screen this appears as horizontal stripes. Consequently, with a liquid crystal display operating at high resolution, the shorter one horizontal period (time T) is made, the less the influence of the rising portion in the drain line waveform can be ignored, and the more marked the horizontal stripes will become.
In Japanese Unexamined Patent Application, First Publication No. Hei 9-15560 (hereafter referred to as the “well-known art”), for those scan lines where the polarity of the write voltage is inverted, the length of one horizontal period is longer than that of the other scan lines. As a result, the difference between the write state when writing with the same polarity and that when writing with the opposite polarity is reduced, and the occurrence of horizontal stripes can be alleviated.
However, to change the length of one horizontal period as in the aforementioned well-known art, the cycle of the clock signal which serves as a reference in the liquid crystal display (hereafter referred to as the “reference clock signal”) must be adjustable. However, in conventional liquid crystal displays, circuit design is performed under the premise that one horizontal period is fixed. Consequently, if the cycle of the reference clock signal is made adjustable, it becomes difficult to avoid making the circuit structure (particularly the circuit block corresponding with the timing controller 107 shown in FIG. 9) more complicated.
Furthermore, the following problem also occurs with the aforementioned well-known art. In short, with the aforementioned well-known art, in the scan lines where the polarity of the write voltage is inverted, the horizontal scanning period is expanded by a predetermined amount of time. However, because the number of scan lines in one frame is fixed and unchangeable, to compensate for the expanded time span, the horizontal scanning periods of the other scan lines must be reduced. For example, because in the above well-known art the polarity of the write voltage is inverted every three lines, of these three scan lines, the horizontal scanning period of two of these scan lines must be shortened.
In order to write image data of the same number of pixels to the liquid crystal cells even though the horizontal scanning period has been reduced, the frequency of a clock signal for taking in the image data (hereafter referred to as the “data intake clock signal”) must be raised. However, in the aforementioned well-known art, the horizontal scanning period of the scan lines where the polarity of the write voltage is inverted is expanded by 1.1–1.4 times. As a result, the operating frequency for each section in the device (in particular the circuit block corresponding with the timing controller 107 and the source driver 106 shown in FIG. 9) must be increased by a considerable amount, and this becomes a hindrance during circuit design and layout design. In addition, as a result of the increase in the operating frequency, it becomes inevitable that EMI (Electro-Magnetic Interference) noise countermeasures will be required.